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Alif Semiconductor /AE722F80F55D5AS_CM55_HP_View /ETH /ETH_MAC_SUB_SECOND_INCREMENT

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Interpret as ETH_MAC_SUB_SECOND_INCREMENT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SSINC

Description

Sub-second Increment Register

Fields

SSINC

Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of CLK_PTP) with the contents of the ETH_MAC_SYSTEM_TIME_NANOSECONDS register. For example, when the PTP clock is 50 MHz (period is 20 ns), the user should program 20 (0x14) when the ETH_MAC_SYSTEM_TIME_NANOSECONDS register has an accuracy of 1 ns (the ETH_MAC_TIMESTAMP_CONTROL[TSCTRLSSR] bit is set). When TSCTRLSSR is cleard, the ETH_MAC_SYSTEM_TIME_NANOSECONDS register has a resolution of ~0.465 ns. In this case, the user should program a value of 43 (0x2B) which is derived by 20 ns/0.465.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data